1. Field of the Invention
The present invention generally relates to liquid crystal display apparatuses, and particularly relates to the driving of gate drivers in an active-matrix-type liquid crystal display apparatus.
2. Description of the Related Art
In an active-matrix-type liquid crystal display (LCD) apparatus, pixels containing thin-film transistors serving as switching devices are arranged in matrix form, with gate bus lines extending in a horizontal direction coupled to the gates of the transistors of the pixels, and data bus lines extending in a vertical direction coupled to the pixel electrodes (capacitors) of the pixels through the transistors. When data is to be displayed on the liquid crystal panel, a gate driver successively drives the gate bus lines one by one to make the transistors conductive with respect to one line at a time. Through the conductive transistors, data for one horizontal line are written from a data driver to the pixels.
FIG. 1 is a diagram showing the construction of a related-art liquid crystal display apparatus.
The liquid crystal display apparatus of FIG. 1 includes a LCD panel 10, a control circuit 11, a gate driver 12, a data driver 13, an inverter circuit 14, and a backlight 15. In the LCD panel 10, pixels including transistors Tr are arranged in matrix form. Gate bus lines GL extending from the gate driver 12 in the horizontal direction are coupled to the gates of the transistors Tr, and data bus lines DL extending from the data driver 13 in the vertical direction serve to write pixel data to the pixel electrodes through the transistors Tr.
An IF signal control circuit 11a of the control circuit 11 receives as incoming signals a clock signal, display data, and a display enable signal indicative of the timing of a display position. A timing controller 11b of the control circuit 11 counts the clock pulses of the clock signal from the start position corresponding to a positive transition of the display enable signal to determine the timing of a horizontal position, thereby generating various control signals. Further, the position where the LOW period of the display enable signal continues for more than a predetermined number of clock pulses is detected, thereby determining the position of the head of each frame.
The control signals supplied to the gate driver 12 from the timing controller 11b include a gate clock signal, a gate start pulse signal, etc. The gate clock signal is a synchronizing signal, and the gate bus lines are driven one by one in synchronization with the positive transitions of the gate clock signal. Namely, the transistors corresponding to one horizontal line for which the gates are turned on are shifted in the vertical direction line by line in synchronization with the positive transitions of the gate clock signal. The gate start pulse signal is a synchronizing signal that indicates the timing at which the first gate bus line is driven. This timing corresponds to the start timing of a frame. Namely, the first gate bus line (one horizontal line) of the screen is selected at the timing indicated by the gate start pulse signal for the writing of display data, and the line to which display data is written is successively shifted in the vertical direction in synchronization with the gate clock signal.
The control signals supplied to the data driver 13 from the timing controller 11b includes a dot clock signal, a data start signal, a latch pulse, etc. The dot clock signal is comprised of clock pulses, and display data are latched by the registers of the data driver 13 in synchronization with the positive transitions of the dot clock signal. The data start signal serves to indicate the start timings of the display data segments that are to be displayed by respective driver circuits 13a provided in the data driver 13. Starting at the timing indicated by the data start signal, the individual registers successively latch display data for one pixel in synchronization with the dot clock signal. The latch pulse serves to indicate the timing at which the display data stored in the registers are latched by a built-in latch. The latched display data signals are converted by DA converters into analog gray-scale signals, which are then output to the data bus lines DL as data bus line drive signals.
A DC/DC converter 11c of the control circuit 11 converts a direct-current power supply voltage into a direct-current voltage having a different level, which is then supplied to each circuit portion. A bias power supply circuit 11d of the control circuit 11 is provided with a highly precise voltage tracking function, and supplies a bias power supply voltage for determining the drive level of the LCD panel 10 to the gate driver 12 and the data driver 13. The inverter circuit 14 generates a high voltage for turning on a cold cathode-ray tube by using the direct-current power supply voltage, and supplies the generated high voltage to the backlight 15. The backlight 15 illuminates the LCD panel 10 from its backside.    [Patent Document 1] Japanese Patent Application Publication No. 5-264962    [Patent Document 2] Japanese Patent Application Publication No. 2002-358051
If the signals of various types as described above are degraded due to noise or the like, it may cause fatal malfunction. When settings are changed to switch the image resolutions of the liquid crystal display or the like, for example, the operation may fall into an abnormal state, resulting in anomalies in the display data signal, the synchronizing signals, the control signals, etc.
For example, the gate start pulse signal, which is a synchronizing signal indicative of the timing at which the first gate bus line is turn on, is normally supplied to the gate driver 12 only once during the period corresponding to the displaying of one frame. When an anomaly occurs due to a change in the settings of the liquid crystal display or the like, however, a plurality of gate start pulse signals may be generated during the period corresponding to the displaying of one frame. Alternatively, the gate start pulse signal may be prolonged so that its pulse width ends up extending over a plurality of horizontal lines.
If the plurality of gate start pulse signals are generated or the pulse width becomes excessively wide, more than one gate bus line is subjected to data writing in the LCD panel 10, resulting in an increase in the power for writing display data in the LCD panel 10. This may increase the load on the power supply circuitry such as the DC/DC converter 11c, causing a system shutdown, or may cause an excessive current to flow in the gate driver 12, which may destroy the circuit.
Accordingly, there is a need for a liquid crystal display apparatus which can prevent the power supply unit and other circuits from suffering a state of excessive load even when anomaly occurs in a gate start pulse.